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atmel at7913e spacewire remote termin al controller (rtc) datasheet features ? leon2-ft sparc v8 processor ? 5 stage pipeline ? 4k instruction caches / 4k data caches ? meiko fpu ? interrupt controller ? uart serial links ? 32-bit timers ? memory interface ? general purpose io ? debug support unit (dsu) ? fifo interface ? adc/dac interface ? 24 channels ? 8bit/16bit wide data bus ? two can interface ? can interface supporting nominal and redundant bus connection ? two bidirectional spacewire links ? rmap support ? full duplex communication ? transmit rate from 1.25 up to 200 mbit/s in each direction ? spacewire link performance ? at 3.3v : 200mbit/s full duplex communication ? jtag interface ? operating range ? voltages ? 1.65v to 1.95v - core ? 3v to 3.6v - i/o ? temperature ? - 55c to +125c ? power consumption : 1w at 50mhz ? radiation performance ? tested up to a total dose of 300 krad (si) according to the mil-std883 method 1019 ? no single event latchup below a let of 80 mev/mg/cm2 ? esd better than 1000v ? quality grades ? qml-q or v with smd 7833g ? ?
atmel at7913e [datasheet] 7833g ? aero ? 04/12 2 ? package: ? 349 pins mcga, mlga ? 352 pins cqfp description the spacewire remote terminal controller (spw-rtc) asic is a single chip embedded system that includes a general purpose leon2-ft sparc v8 core with a meiko fp unit (ieee-754). this architecture provides the mi xed capability to effectively perform data handling at platform level and powerful dat a processing at payload level. the spw-rtc includes both can and spacewire interfaces which allows bridging traffic from sensor networks onto a high data rate spacewire network. its edac protected fifo and memory interfaces allows in terfacing towards peripheral i/o t hat may perform specialised data processing tasks. the spacewire-rtc device includes an embedde d microprocessor, a can bus controller, adc/dac interfaces for analogue acquisit ion/conversion, standard interfaces and resources (uarts, timers, general purpose input output). the spacewire-rtc device can be operated st and-alone or with a number of external devices such as sram, prom and fifo memories, adc and dac converters. the device can be managed locally by the on-chip processor, or remotely via its spacewire link interfaces. spacewire-rtc device can operate as a single-chip system, with software being uploaded to its on-chip memory via the spacewire link interface, forming a compact solution for remotely controlled applications. or it can operate in a full-size system, with software being decompressed from local prom and executed from multiple fast and wide sram memory banks. the device provides scalabi lity in terms of use of external devices and operating frequency. figure 1. at7913e spacewre rtc block diagram
atmel at7913e [datasheet] 7833g ? aero ? 04/12 3 table of contents 1. pin description.....................................................................................4 1.1 system .............................................................................................................. 4 1.2 can interf ace.................................................................................................... 4 1.3 adc/dac inte rface ........................................................................................... 5 1.4 memory interface .............................................................................................. 5 1.5 fifo interface ................................................................................................... 6 1.6 spacewire in terface.......................................................................................... 6 1.7 jtag 7 1.8 power supply .................................................................................................... 7 2. architecture..........................................................................................9 2.1 leon2-ft pr ocessor ........................................................................................ 9 2.2 debug suppor t unit ......................................................................................... 10 2.2.1 debug suppor t unit .......................................................................... 10 2.2.2 debug communica tion li nk................................................................ 10 2.3 leon2-ft peri pheral s.................................................................................... 10 2.3.1 interrupt c ontrolle r ............................................................................ 10 2.3.2 32-bit ti mer....................................................................................... 10 2.3.3 uart serial links ............................................................................ 10 2.3.4 16-bit general purpos e input ou tput ................................................ 11 2.3.5 memory interface.............................................................................. 11 2.4 on-chip me mory............................................................................................. 11 2.5 fifo inte rface ................................................................................................. 11 2.6 adc/dac inte rface ......................................................................................... 11 2.7 32-bit ti mers ................................................................................................... 12 2.8 24-bit general purpos e input ou tput .............................................................. 12 2.9 can interf ace.................................................................................................. 12 2.10 spacewire link interfac e ................................................................................ 12 2.11 jtag inte rface ................................................................................................ 13 3. typical applications ...........................................................................14 3.1 at7913e in icu .............................................................................................. 14 3.2 at7913e in obc............................................................................................. 14 3.3 at7913e on pay load....................................................................................... 14 4. package information ..........................................................................15 4.1 packages ou tline ............................................................................................ 15 4.1.1 mcga 349 out line ............................................................................ 15 4.1.2 qfp 352 out line................................................................................ 16 4.2 pin assign ment ............................................................................................... 17 4.2.1 power and ground ............................................................................ 17 4.2.2 system and pe ripheral s.................................................................... 18 4.2.3 unconnected pins ............................................................................. 21 5. electrical characteristics....................................................................22 5.1 absolute maximu m rating s ............................................................................ 22 5.2 operating range............................................................................................. 22 5.3 dc characteri stics ........................................................................................... 23 5.4 ac characte ristics ........................................................................................... 23 5.5 timing diagr ams ............................................................................................. 24 6. ordering information ..........................................................................25 6.1 at7913e orderi ng codes ............................................................................... 25
atmel at7913e [datasheet] 7833g ? aero ? 04/12 4 1. pin description 1.1 system sysclk ? input system clock sysresetn - input system reset leonerrorn - io, open-drain, output leon error - this active low output is asserted when the processor has entered error state and is halted. this happens when traps are disabled and an synchronous (un-maskable) trap occurs. leonwdn - io, open-drain, output leon watchdog - this active low output is asserted when the watchdog times-out. leondsuen - input dsu enable - the active high input enables the dsu unit. if de-asserted, the dsu trace buffer will continue to operate but the processor will not enter debug mode. leondsutx ? output dsu uart transmit - this active high output provides the data from the dsu communication link transmitter leondsurx - input dsu uart receive - this active high input provides the data to the dsu communication link receiver. leondsubre - input dsu break - a low-to-high transition on this active high input will generate break condition and put the processor in debug mode leondsuact ? output dsu active - this active high output is asserted when the processor is in debug mode and controlled by the dsu. leonpio[15:0] - io leon parallel input / output - these bi-directional signals can be used as inputs or outputs to control external devices. gpio[23:0] - io general purpose input / output timeclk - input external timer clock timetrig[2:1] ? output external timer trigger - asserted for 8 system clock periods 1.2 can interface cantx[1:0] ? output can transmit canrx[1:0] - input can receive
atmel at7913e [datasheet] 7833g ? aero ? 04/12 5 canen[1:0] ? output can transmit enable 1.3 adc/dac interface addata[15:0] - io adc/dac data adaddr[7:0] - io adc/dac address adwr - output dac write strobe adcs - output adc chip select adrc - output adc read/convert adrdy - input adc ready adtrig - input adc trigger 1.4 memory interface mema[22:0] ? output memory interface address - these active high outputs carry the address during accesses on the memory bus. when no access is performed, the address of the last access is driven (also internal cycles). memd[31:0] - io memory interface data - memd[31:0] carries the data during transfers on the memory bus. the processor only drives the bus during write cycles. during accesses to 8-bit areas, only memd[31:24] are used. memcb[7:0] - io memory interface checkbits memcb[6:0] carries the edac checkbits, memcb[7] takes the value of tb[7] in the error control register. the processor only drive memcb[7:0] duri ng write cycles to areas programmed to be edac protected memcsn[3:0] ? output sram chip select - these active low signals provide an individual output enable for each sram bank. memoen[3:0] ? output sram output enable -these active low outputs provide the chip-select signals for each sram bank. memwrn[3:0] ? output sram byte write strobe - these active low outputs provide individual write strobes for each byte lane. memwrn[0] controls memd[31:24], memwrn[1] controls memd[23:16], etc. romcsn[1:0] ? output prom chip select - these active low outputs provide the chip-select signal for the prom area. romcsn[0] is asserted when the lower half of the prom area is accessed (0 - 0x10000000), while romcsn[1] is asserted for the upper half.
atmel at7913e [datasheet] 7833g ? aero ? 04/12 6 iocsn ? output i/o area chip select - this active low output is the chip-select signal for the memory mapped i/o area. iooen ? output i/o area output enable - this active low output is asserted during read cycles on the memory bus. ioread ? output i/o area read - this active high output is asserted during read cycles on the memory bus. iowrn ? output i/o area write - this active low output provides a write strobe during write cycles on the memory bus. iobrdyn - input i/o area ready - this active low input indicates that the access to a memory mapped i/o area can be terminated on the next rising clock edge. membexcn -input memory exception - this active low input is sampled simultaneously with the data during accesses on the memory bus. if asserted, a memory error will be generated. 1.5 fifo interface fifod[15:0] - io fifo data fifop[1:0] - io fifo parity fifordn - output fifo read strobe fifowrn ? output fifo write strobe fifofulln - input fifo full fifoempn - input fifo empty fifohalfn - input fifo half-full, half-empty 1.6 spacewire interface spwclksrc - input spacewire transmitter clock source spwclkmult[1:0] - input spacewire clock configuration spwclk10mbit[2:0] - input spacewire clock configuration spwclkpllcnfg[2:0] - input
atmel at7913e [datasheet] 7833g ? aero ? 04/12 7 spacewire clock configuration spwclkmuxsel - input spacewire clock configuration - configuration external clock when 1, internal pll when 0. spwdin_p[1:0] - input, lvds positive spacewire data input, positive spwdin_n[1:0] - input, lvds negative spacewire data input, negative spwsin_p[1:0] - input, lvds positive spacewire strobe input, positive spwsin_n[1:0] - input, lvds negative spacewire strobe input, negative spwdout_p[1:0] - output, lvds positive spacewire data output, positive spwdout_n[1:0] - output, lvds negative spacewire data output, negative spwsout_p[1:0] - output, lvds positive spacewire strobe output, positive spwsout_n[1:0] - output, lvds negative spacewire strobe output, negative lvdsref[0:1] - power lvds reference voltage for spacewire channels 1.7 jtag taptrst - test reset tap reset - resets the test state machine. can be asynchronous with tck. shall be grounded for end application taptck - test clock tap clock - used to clock serial data into boundary scan latches and control sequence of the test state machine. tck can be asynchronous with clk taptms - test mode select tap mode select - resets the test state machine. can be asynchronous with tck. shall be grounded for end application. taptdi - test data input tap data input - serial input data to the boundary scan latches. synchronous with tck. taptdo - test data output tap data output - serial output data from the boundary scan latches. synchronous with tck 1.8 power supply vda ? 1.8v power supply vda is the power supply input for the at7913e core.
atmel at7913e [datasheet] 7833g ? aero ? 04/12 8 pvddpll ? 1.8v pll power supply vda is the power supply input for the at7913e pll. vdb ? 3.3v power supply vdb is the power supply input for the at7913e ios. vsa, vsb, pvsspll - ground
atmel at7913e [datasheet] 7833g ? aero ? 04/12 9 2. architecture the at7913e spacewire remote terminal controller (rtc) is a bridge between the spacewire network and the can bus. the at7913e is based on a leon2-ft sparc v8 processor core together with a wide range of interfaces including : ? debug support unit ? leon2-ft peripherals ? interrupt controller ? 32-bit timer ? uart serial links ? 16-bit general purpose input output ? memory interface ? on-chip memory ? fifo interface ? adc/dac interface. ? 32-bit timers ? 24-bit general purpose input output ? can interface ? spacewire link interface ? jtag interface 2.1 leon2-ft processor the spacewire-rtc asic includes the leon2-ft integer unit (iu) and the meiko floating point unit (fpu). the leon2-ft iu implements the sparc integer instruction set as defined in the sparc architecture manual version 8. the leon2-ft iu has the following features: ? 5-stage instruction pipeline ? separate instruction and data cache interface ? support for 8 register windows ? multiplier 16x16 ? radix-2 divider (non-restoring) to allow for software compatibility with existing devices such as the at697e from atmel, the at7913e spacewire-rtc includes all standard leon2-ft peripherals and the debug support unit. the programming model of the spacewire-rtc device is thus compatible with the existing devices, only requiring support for the additional functions and interfaces to be added to the existing software development tools and operating systems. the spacewire-rtc includes a leon2-ft core with 4kbyte instruction and data caches. it also includes a meiko fpu (the same one as included in the atmel at697device).
atmel at7913e [datasheet] 7833g ? aero ? 04/12 10 2.2 debug support unit the at7913e spacewire rtc includes a hardware debug suppor t to aid software debugging on target hardware. the support is provided through two modules: ? a debug support unit (dsu) ? a debug communication link 2.2.1 debug support unit the dsu can put the processor in debug mode, allowing read/write access to all processor registers and cache memories. the dsu also contains a trace buffer which stores executed instructions and/or data transfers on the amba ahb bus. the debug support unit is used to control the trace buffer and the processor debug mode. the dsu is attached to the ahb bus as slave, occupying a 2 mbyte address space. through this address space, any ahb master can access the processor registers and the contents of the trace buffer. the dsu control registers can be accessed at any time, while the processor registers and caches can only be accessed when the processor has entered debug mode. the trace buffer can be accessed only when tracing is disabled/completed. in debug mode, the processor pipeline is held and the processor state can be accessed by the dsu. 2.2.2 debug communication link the spacewire-rtc device includes a deb ug support unit communication link that consists of a uart connected to the ahb bus as a master. the debug communications link implements a simple read/write protocol and uses standard asynchronous uart communications. the simple communication protocol is supported to transmit access parameters and data. a link command consists of a control byte, followed by a 32-bit address, followed by optional write data. 2.3 leon2-ft peripherals the at7913e spacewire-rtc includes al l the standard leon2-ft peripherals. 2.3.1 interrupt controller the interrupt controller is used to priorities and propagate interrupt requests from internal or external devices to the integer unit. 15 interrupts are handled, divided on two priority levels. a secondary interrupt controller is included to support the 32 additional interrupts used by the additional on-chip peripherals of the at7913e device. 2.3.2 32-bit timer the timer unit implements two 32-bit timers, one 32-bit watchdog and one 10-bit shared prescaler. the functionality of the timers has not been modified with respect to existing implementations, to allow for software compatibility. the watchdog functionality is used for overall software timeout handling and is the basis for error management. 2.3.3 uart serial links two identical uarts are provided for serial communicati ons. the uarts support data frames with 8 data bits, one optional parity bit and one stop bit. to generate the bit-rate, each uart has a programmable 12-bits clock divider. hardware flow-control is supported through handshake signals.
atmel at7913e [datasheet] 7833g ? aero ? 04/12 11 2.3.4 16-bit general purpose input output the 16-bit general purpose input output port can be individually programmed as output or input. two registers are associated with the operation of the port; the combined input/output register, and direction register. when read, the input/output register will return the current value of the port; when written, the value will be driven on the port signals. the direction register defines the direction for each individual port. 2.3.5 memory interface the spacewire-rtc memory interface is implemented using the leon2-ft memory controller that supports the following: ? 8-bit prom with sequential edac, ? 8-bit sram with sequential edac ? 32-bit prom/sram with parallel-edac ? 8, 16, 32 bit i/o without-edac (wait-state and/or ready handshake) ? 16 bit gpio (byte-wise) when less than 32 bit memory used 2.4 on-chip memory the spacewire-rtc device includes a fault tolerant on-c hip sram with embedded error detection and correction (edac) and amba ahb slave interface. one error is corrected and two errors are detected, which is done by using a (32, 7) bch code. some of the features available are single error counter, diagnostic reads and writes and auto-scrubbing (automatic correction of single errors during reads). the on-chip memory comprises a 32-bit wide memory bank of 64 kbytes of data. 2.5 fifo interface this fifo memory can be accessed as an on-chip memory or as an external interface of the chip via the memory interface. the fifo interface supports transmission and reception of blocks of data by use of circular buffers located in memory external to the core. separate transmit and receive buffers are assumed. reception and transmission of data can be ongoing simultaneously. 2.6 adc/dac interface the spacewire-rtc includes a combined analogue-to-digital converter (adc) and digital-to-analogue converter (dac) interface. the adc/dac interface provides a combined signal interface to parallel adc and dac devices. the two interfaces are merged both at the pin/pad level as well as at the interface towards the amba bus. the interface supports simultaneously one adc device and one dac device in parallel. address and data signals unused by the adc and the dac can be use for general purpose input output, providing 0, 8, 16 or 24 channels. the adc interface supports 8 and 16 bit data widths. it provides chip select, read/convert and ready signals. the timing is programmable. it also provides an 8-bit address output. the adc conversion can be initiated either via the amba interface or by internal or external triggers. an interrupt is generated when a conversion is completed. the dac interface supports 8 and 16 bit data widths. it provides a write strobe signal. the timing is programmable. it also provides an 8-bit address output.
atmel at7913e [datasheet] 7833g ? aero ? 04/12 12 2.7 32-bit timers the spacewire-rtc includes a general purpose timer unit that implements one prescaler and two 32-bit decrementing timers. 2.8 24-bit general purpose input output the spacewire-rtc includes a 24-bit general purpose input output core. the amba apb bus is used for control and status handling. the core provides 24 channels. each channel is individually programmed as input or output. additionally, 8 of the channels are also programmable as pulse command outputs. the default reset configuration for each channel is as input. the default reset value each channel is logical zero. the pulse command outputs have a common 20-bit counter for establishing the pulse command length. the pulse command length defines the logical one (active) part of the pulse. it is possible to select which of the channels shall generate a pulse command. the pulse command outputs are generated simultaneously in phase with each other, and with the same length (or duration). it is not possible to generate pulse commands out of phase with each other. 2.9 can interface the spacewire-rtc includes a can controller. the can protocol is based on the esa hurricane can controller vhdl core. the controller uses the amba apb bus for configuration, c ontrol and status handling. the amba ahb bus is used for retrieving and storing can messages in memory external to the can controller. this memory can be located on-chip or external to the chip. the can controller supports transmission and reception of sets of messages by use of circular buffers located in memory external to the core. separate transmit and receive buffers are assumed. reception and transmission of sets of messages can be ongoing simultaneously. 2.10 spacewire link interface the spacewire (spw2) module is used for transmitting and re ceiving data over a spacewire link. it provides support for transmitting any type of protocol or data structure using spacewire packets. it provides hardware support for receiving two types of spacewire transfer protocols, and can relay packets of other protocols to software. the spacewire virtual channel trans fer protocol (vctp) implements multiple virtual channels (only one implemented in spacewire-rtc) on a single spacew ire link. the remote memory access protocol (rmap) implements remote memory access to resources in the node via the spacewire link. data received over the link by the spacewire codec are temporarily stored in an rxfifo. data are then stored to memory by the spacewire module via direct memoryaccess. multiple virtual receive channels (rxvc) can be used, each with its private memory area to which data are written. in spacewire-rtc one channel (rxvc(1)) is used for storing vctp packets, and one channel (rxvc(0)) is used for storing rmap responses, rmap commands not supported by hardware and packets of other types of transfer protocols. all rxvc share the same link. the spacewire module implements hardware support for the rmap. rmap is used for remotely accessing resources on the local amba bus. the rmap implementation can receive commands and generate responses, utilizing the aforementioned rxfifo and the txfifo.
atmel at7913e [datasheet] 7833g ? aero ? 04/12 13 data to be sent are read by the spacewire module from memory via direct memory access. data are then temporarily stored in a txfifo when forwarded to the spacewire codec for transmission over the link. multiple virtual transmit channels (txvc) can be used, each with its private send list stored in memory from which data are read. in spacewire- rtc one channel (txvc(0)) is used for automatic rmap responses, and another channel (txvc(1)) is used for transmissions set up by the user. all txvc share the same link. rmap responses have priority over transmissions set up by the user. the arbitration is performed for each packet sent. 2.11 jtag interface the jtag interface (compliant with ieee-std-1149.1) is used for the purpose of boundary scan testing during manufacture and test of printed circuit boards hosting the asic.
atmel at7913e [datasheet] 7833g ? aero ? 04/12 14 3. typical applications the capabilities of the spacewire-rtc device are not limited to support the can bus in the instrument controller unit (icu), but also allows it to be used in an on-board computer (obc). the at7913e spacewire rtc is perfectly suited for application requiring cost optimizations as it can be used in both payload and avionics. 3.1 at7913e in icu the spacewire-rtc device can be integrated in the instrument controller unit (icu) that acts as the payload data processor and mainly receives payload data from instruments and produces processed data to be down linked. the main data communication is performed via the spacewire network. the icu is however controlled and monitored via the can network from the on-board computer (obc). 3.2 at7913e in obc the can controller in the spacewire-rtc device acts as a remote terminal that is being managed by the obc. alternatively, the spacewire-rtc device can be integrated in the on-board computer (obc). since the obc acts as the network manager on the can network, the can controller carters capability such as node management and time distribution. the obc also communicates or manages the spacewire network via spacewire links. 3.3 at7913e on payload the main application of the spacewire-rtc device is however in instruments or individual experiments of the payload. it provides an abundance of interfaces, each with a high degree of programmability and configurability. it is able to acquire analogue and digital data, generated by connected peripherals and to generate discrete commands towards the same peripherals.
atmel at7913e [datasheet] 7833g ? aero ? 04/12 15 4. package information 4.1 packages outline 4.1.1 mcga 349 outline figure 4-1. mechanical description package lid is connected to ground
atmel at7913e [datasheet] 7833g ? aero ? 04/12 16 4.1.2 qfp 352 outline table 4-1. mechanical description package lid is connected to ground
atmel at7913e [datasheet] 7833g ? aero ? 04/12 17 4.2 pin assignment 4.2.1 power and ground table 4-2. power and ground pin assignement pin name packages pin name packages pin name packages pin name packages qfp352 mcga349 qfp352 mcga349 qfp352 mcga349 qfp352 mcga349 vda 8 v17 vsa 7 v18 vdb 16 g12 vsb 17 d12 vda 82 v16 vsa 81 v4 vdb 24 f10 vsb 25 h10 vda 96 c18 vsa 95 d1 vdb 31 w8 vsb 32 p8 vda 170 c19 vsa 169 d19 vdb 41 w9 vsb 42 u8 vda 184 u1 vsa 183 t1 vdb 63 u10 vsb 64 r10 vda 272 u2 vsa 257 t19 vdb 91 v11 vsb 92 u11 vda 346 u18 vsa 271 u3 vdb 118 m11 vsb 119 v12 vda 258 u19 vsa 345 u17 vdb 127 w13 vsb 128 r14 vda v3 vsa v2 vdb 134 t14 vsb 135 u15 vda w17 vsa w16 vdb 141 n13 vsb 142 r18 vda w3 vsa w4 vdb 150 p18 vsb 151 p14 vda b17 vsa b18 vdb 157 m12 vsb 158 n18 vda a3 vsa a4 vdb 165 a8 vsb 166 h9 vda a17 vsa a16 vdb 175 m13 vsb 179 m16 vda b3 vsa b2 vdb 200 k14 vsb 188 k12 vda b4 vsa b16 vdb 215 j15 vsb 195 k18 vda c1 vsa c3 vdb 223 j16 vsb 202 j14 vda c2 vsa c17 vdb 231 g15 vsb 217 h16 vdb 239 f17 vsb 224 g16 vdb 249 f18 vsb 233 g14 pvddpll 279 a14 vdb 256 g7 vsb 240 b5 pvsspll 280 f14 vdb 267 d17 vsb 250 f13 vdb 288 f1 vsb 259 h8 vdb 303 j8 vsb 268 h3 vdb 349 h6 vsb 290 d2 vdb 187 k6 vsb 305 h7 vdb 324 m2 vsb 325 j6 vdb 194 v5 vsb 351 k8 vsb n5 vsb t3
atmel at7913e [datasheet] 7833g ? aero ? 04/12 18 4.2.2 system and peripherals table 4-3. system and spacewire pin name packages pin name packages pin name packages qfp352 mcga349 qfp352 mcga349 qfp352 mcga349 sysclk 83 r1 spwclk10mbit_0 306 a10 spwdin_n_0 300 c11 sysresetn 84 r4 spwclk10mbit_1 307 e11 spwdin_n_1 212 l17 taptck 310 e10 spwclk10mbit_2 308 d10 spwdin_p_0 299 b11 taptdi 313 g10 spwclkmult_0 281 d13 spwdin_p_1 211 l18 taptdo 312 b10 spwclkmult_1 282 h12 spwdout_n_0 293 e13 taptms 309 c10 spwclkmuxsel 287 h11 spwdout_n_1 205 n15 taptrstn 311 e9 spwclkpllcnfg_0 284 c14 spwdout_p_0 291 b12 testmode 19 spwclkpllcnfg_1 285 a13 spwdout_p_1 203 m18 testse 40 spwclkpllcnfg_2 286 e14 spwsin_n_0 302 c12 timeclk 44 j5 spwclksrc 283 b13 spwsin_n_1 214 m17 timetrig_1 45 k4 spwsin_p_0 301 a11 timetrig_2 46 k3 lvdsref0 298 d11 spwsin_p_1 213 l19 leondsuact 117 r7 lvdsref1 210 l16 spwsout_n_0 296 f12 leondsubre 116 v8 spwsout_n_1 208 m14 leondsuen 113 n8 spwsout_p_0 294 a12 leondsurx 115 u7 spwsout_p_1 206 m19 leondsutx 114 t8 leonerrorn 85 m7 leonwdn 87 n7
atmel at7913e [datasheet] 7833g ? aero ? 04/12 19 table 4-4. memory interface pin name packages pin name packages pin name packages pin name packages qfp352 mcga349 qfp352 mcga349 qfp352 mcga349 qfp352 mcga349 mema_0 120 p9 memd_0 182 t17 memd_23 236 h19 romcsn_0 155 n11 mema_1 121 r8 memd_1 185 r19 memd_24 237 j12 romcsn_1 156 p12 mema_2 124 n9 memd_2 186 r16 memd_25 238 h18 memcsn_0 172 t15 mema_3 125 v9 memd_3 189 p16 memd_26 241 g17 memcsn_1 173 n12 mema_4 126 u9 memd_4 191 p19 memd_27 242 j13 memcsn_2 180 t16 mema_5 129 p10 memd_5 192 t18 memd_28 243 h14 memcsn_3 181 n14 mema_6 130 m10 memd_6 193 n16 memd_29 247 f15 memoen_0 164 p13 mema_7 131 w10 memd_7 196 p17 memd_30 248 g18 memoen_1 167 v14 mema_8 132 r9 memd_8 197 n19 memd_31 251 j11 memoen_2 168 u16 mema_9 133 t10 memd_9 198 p15 memoen_3 171 w15 mema_10 136 r11 memd_10 199 l12 memcb_0 252 f19 memwrn_0 159 v13 mema_11 137 v10 memd_11 218 k19 memcb_1 253 d18 memwrn_1 160 u14 mema_12 138 n10 memd_12 219 l15 memcb_2 254 f16 memwrn_2 161 t13 mema_13 139 w11 memd_13 220 k16 memcb_3 255 e17 memwrn_3 162 l11 mema_14 140 u12 memd_14 221 k17 memcb_4 260 e19 membexcn 276 d14 mema_15 145 t11 memd_15 222 k15 memcb_5 261 e16 iobrdyn 269 d16 mema_16 146 p11 memd_16 225 k13 memcb_6 262 h13 iocsn 275 c16 mema_17 147 l10 memd_17 226 j19 memcb_7 263 g13 iooen 274 b14 mema_18 148 r12 memd_18 227 h17 ioread 273 d15 mema_19 149 w12 memd_19 228 j18 iowrn 270 a15 mema_20 152 r13 memd_20 230 j17 mema_21 153 t12 memd_21 234 k11 mema_22 154 u13 memd_22 235 h15
atmel at7913e [datasheet] 7833g ? aero ? 04/12 20 table 4-5. other peripherals pin name packages pin name packages pin name packages pin name packages qfp352 mcga349 qfp352 mcga349 qfp352 mcga349 qfp352 mcga349 adaddr_0 47 k5 fifod_0 18 g4 gpio_0 314 a9 leonpio_0 93 p7 adaddr_1 48 l5 fifod_1 20 g2 gpio_1 317 b9 leonpio_1 94 t4 adaddr_2 49 k2 fifod_10 33 h5 gpio_2 318 c9 leonpio_2 97 w5 adaddr_3 50 k7 fifod_11 36 j7 gpio_3 319 d9 leonpio_3 98 t5 adaddr_4 51 l1 fifod_12 37 j2 gpio_4 320 f9 leonpio_4 99 v6 adaddr_5 52 m3 fifod_13 38 j3 gpio_5 322 j10 leonpio_5 100 u4 adaddr_6 53 l2 fifod_14 39 j1 gpio_6 323 e8 leonpio_6 101 t6 adaddr_7 54 l3 fifod_15 43 k1 gpio_7 326 b8 leonpio_7 104 w6 adcs 79 p2 fifod_2 21 f3 gpio_8 327 e7 leonpio_8 105 p6 addata_0 59 k9 fifod_3 22 g1 gpio_9 328 d8 leonpio_9 106 t7 addata_1 60 m5 fifod_4 23 f5 gpio_10 329 c7 leonpio_10 107 m8 addata_10 71 n2 fifod_5 26 h4 gpio_11 330 g9 leonpio_11 108 v7 addata_11 72 p3 fifod_6 27 g3 gpio_12 331 f8 leonpio_12 109 u6 addata_12 73 n4 fifod_7 28 h2 gpio_13 332 a7 leonpio_13 110 w7 addata_13 74 l9 fifod_8 29 g5 gpio_14 333 e6 leonpio_14 111 r6 addata_14 76 t2 fifod_9 30 h1 gpio_15 334 b7 leonpio_15 112 m9 addata_15 77 p4 fifoempn 6 d3 gpio_16 335 c6 addata_2 61 m1 fifofulln 5 g6 gpio_17 336 d7 canen_0 3 e2 addata_3 62 l8 fifohalfn 9 e1 gpio_18 337 j9 canen_1 4 d4 addata_4 65 m4 fifop_0 12 f6 gpio_19 338 a6 canrx_0 347 d5 addata_5 66 n3 fifop_1 13 f4 gpio_20 339 f7 canrx_1 348 g8 addata_6 67 l7 fifordn 11 f2 gpio_21 340 d6 cantx_0 343 c4 addata_7 68 m6 fifowrn 10 e4 gpio_22 341 c5 cantx_1 344 a5 addata_8 69 n1 gpio_23 342 b6 addata_9 70 p5 adrc 80 n6 adrdy 57 l4 adtrig 58 l6 adwr 78 r3
atmel at7913e [datasheet] 7833g ? aero ? 04/12 21 4.2.3 unconnected pins table 4-6. unconnected pins pin name packages pin name packages pin name packages pin name packages qfp352 mcga349 qfp352 mcga349 qfp352 mcga349 qfp352 mcga349 nc 1 b15 nc 102 k10 nc 209 w14 nc 292 nc 2 c8 nc 103 l13 nc 216 nc 295 nc 14 c13 nc 143 l14 nc 229 nc 297 nc 15 c15 nc 144 m15 nc 232 nc 304 nc 34 e3 nc 163 p1 nc 244 nc 315 nc 35 e5 nc 174 n17 nc 245 nc 316 nc 55 e12 nc 176 r2 nc 246 nc 321 nc 56 e15 nc 177 r5 nc 264 nc 350 nc 75 e18 nc 178 r15 nc 265 nc 352 nc 86 f11 nc 190 r17 nc 266 nc 122 nc 88 g11 nc 201 t9 nc 277 nc 123 nc 89 g19 nc 204 u5 nc 278 nc 90 j4 nc 207 v15 nc 289
atmel at7913e [datasheet] 7833g ? aero ? 04/12 22 5. electrical characteristics 5.1 absolute maximum ratings table: absolute rating ltside supply voltage i/os (vdb buffers) ??............................ -0.3v to +4v supply voltage core (vda arra y)..............????.........-0.3v to +2v storage temperature ................. ............... ............... ... -65 c to +150 c input/ output voltages with respect to ground...... ............. -0.3v to 4v power dissipation ..........................................................................2w esd for i/o ..... ................ ............... ............... ............... ............> 2000v esd for pll ?..... ............... ............... .............. ............. ............> 1000v *notice: stresses at or above those listed under "absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the devic e at these or any other conditions beyond those indicated in the operational sections of this specification are not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability 5.2 operating range table 5-1. operating range operating temperature -55 c to +125 c vdb ? io power supply 3.3v 0.3v vda - core power supply 1.8v 0.15v
atmel at7913e [datasheet] 7833g ? aero ? 04/12 23 5.3 dc characteristics table 5-2. dc characteristics symbol parameter test condition min typ max units vca operating voltage 1.65 1.8 1.95 v vcb 3 3.3 3.6 v vih input high voltage 2 v vil input low voltage 0.8 v iil low level input current vin = gnd -1 1 a iilpd low level input pull-down current vin = gnd -5 5 a iilpu low level input pull-up current vin = gnd -110 a iih high level input current vin = vcb (max) -1 1 a iihpu high level input pull-up current vin = vcb (max) -5 5 a iihpd high level input pull-down current vin = vcb (max) 600 a iozl output leakage low current vout = gnd -1 a iozh output leakage high current vout = vcb (max) 1 a voh output high voltage iol = 2, 4, 8, 12, 16ma / vcc = vcb(min) vcc-0.4 v vol output low voltage ioh = 2, 4, 8, 12, 16ma / vcc = vcb(min) 0.4 v ios output short circuit current vout = vcb 23 ma vod differential output delay 247 454 mv vos common mode output voltage 1125 1375 mv iccsba supply current for array when not clocked vca(max) 3.5 ma iccopa operating supply current for array vca(max) 52 ma 5.4 ac characteristics the following table gives the worst case timings measured by atmel on the 3.0v to 3.6v operating range table 5-3. 3.3v operating range timings parameter symbol min. max. unit propagation delay, sysclk rising to memcsn falling tp0 18 ns propagation delay, sysclk rising to cantx rising tp1 29 ns propagation delay, sysclk rising to gpio rising tp2 25 ns propagation delay, sysclk rising to fifod rising tp3 16 ns propagation delay, spwclksrc rising to spwdout_p falling tp4 14 ns propagation delay, spwclksrc rising to spwdout_n_0 rising tp5 14 ns
atmel at7913e [datasheet] 7833g ? aero ? 04/12 24 5.5 timing diagrams figure 5-1. static ram read cycle (0 waitsate) figure 5-2. fifod, gpio and can_tx clock delay figure 5-3. clock to spacewire data out delay
atmel at7913e [datasheet] 7833g ? aero ? 04/12 25 6. ordering information 6.1 at7913e ordering codes atmel ordering code package type temperature range quality level at7913e-2h-e mcga349 25c engineering sample 5962-10a0301qxb mcga349 -55c to +125c qmlq 5962-10a0301vxb mcga349 -55c to +125c qmlv 5962r10a0301vxb mcga349 -55c to +125c qmlv-rha at7913e-2u-e lga349 25c engineering sample 5962-10a0301qyc lga349 -55c to +125c qmlq 5962-10a0301vyc lga349 -55c to +125c qmlv 5962r10a0301vyc lga349 -55c to +125c qmlv-rha at7913e-yc-e cqfp352 25c engineering sample at7913e-yc-mq* cqfp352 -55c to +125c qmlq at7913e-yc-sv* cqfp352 -55c to +125c qmlv (1) preliminary ordering code waiting for smd reference
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